From f5769d48c901d5091eb1911cc88808681ad3dd5c Mon Sep 17 00:00:00 2001 From: Marvin Blum Date: Sun, 16 Apr 2017 13:46:18 +0200 Subject: [PATCH] Chip config. --- ard/pins.c | 4 +- main.c | 14 +++-- rf24/nRF24L01.h | 134 ++++++++++++++++++++++++++++++++++++++++++------ rf24/rf24.c | 72 ++++++++++++++++++++++++-- rf24/rf24.h | 5 +- 5 files changed, 201 insertions(+), 28 deletions(-) diff --git a/ard/pins.c b/ard/pins.c index 48e44d2..dc39841 100644 --- a/ard/pins.c +++ b/ard/pins.c @@ -8,8 +8,8 @@ const unsigned char INPUT = 0x00; const unsigned char OUTPUT = 0x01; // analog pins (digital range from 0 to 13) -const unsigned char A0 = 0x0e; -const unsigned char A1 = 0x0f; +const unsigned char A0 = 0x0E; +const unsigned char A1 = 0x0F; const unsigned char A2 = 0x10; const unsigned char A3 = 0x11; const unsigned char A4 = 0x12; diff --git a/main.c b/main.c index ddc76ff..948ccc5 100644 --- a/main.c +++ b/main.c @@ -6,6 +6,9 @@ #include "rf24/rf24.h" #include "rf24/nRF24L01.h" +unsigned char rx_addr[5] = {0xE7, 0xE7, 0xE7, 0xE7, 0xE7}; +unsigned char tx_addr[5] = {0xD7, 0xD7, 0xD7, 0xD7, 0xD7}; + void prepare(); void loop(); @@ -21,12 +24,17 @@ void prepare(){ pins_init(); serial_init(9600); - _delay_ms(50); + _delay_ms(200); rf24_init(7, 6, 5, 4, 3, 2); _delay_ms(200); + rf24_config(0x02, 0xFF); + _delay_ms(200); + rf24_rx_addr(rx_addr); + _delay_ms(200); + rf24_tx_addr(tx_addr); + _delay_ms(200); } void loop(){ - rf24_read_register(STATUS); - _delay_ms(5); + _delay_ms(20); } diff --git a/rf24/nRF24L01.h b/rf24/nRF24L01.h index bb5e445..b86c26a 100644 --- a/rf24/nRF24L01.h +++ b/rf24/nRF24L01.h @@ -1,25 +1,125 @@ #ifndef NRF24L01_H_ #define NRF24L01_H_ -#define CONFIG 0x00 -#define MASK_RX_DR 6 -#define MASK_TX_DS 5 -#define MASK_MAX_RT 4 -#define EN_CRC 3 -#define CRCO 2 -#define PWR_UP 1 -#define PRIM_RX 0 +#define CONFIG 0x00 +#define MASK_RX_DR 6 +#define MASK_TX_DS 5 +#define MASK_MAX_RT 4 +#define EN_CRC 3 +#define CRCO 2 +#define PWR_UP 1 +#define PRIM_RX 0 -#define STATUS 0x07 -#define RX_DR 6 -#define TX_DS 5 -#define MAX_RT 4 -#define RX_P_NO 3 // 3 bits -#define TX_FULL 0 +#define EN_AA 0x01 +#define ENAA_P5 5 +#define ENAA_P4 4 +#define ENAA_P3 3 +#define ENAA_P2 2 +#define ENAA_P1 1 +#define ENAA_P0 0 -#define R_REGISTER 0x00 -#define W_REGISTER 0x20 -#define REG_MASK 0x1f +#define EN_RXADDR 0x02 +#define ERX_P5 5 +#define ERX_P4 4 +#define ERX_P3 3 +#define ERX_P2 2 +#define ERX_P1 1 +#define ERX_P0 0 + +#define SETUP_AW 0x03 +#define AW 0 // 2 bits + +#define SETUP_RETR 0x04 +#define ARD 4 // 4 bits +#define ARC 0 // 4 bits + +#define RF_CH_REG 0x05 +#define RF_CH 0 // 7 bits +#define RF_CH_MASK 0x7F + +#define RF_SETUP 0x06 +#define CONT_WAVE 7 +#define RF_DR_LOW 5 +#define PLL_LOCK 4 +#define RF_DR_HIGH 3 +#define RF_PWR 0 // 2 bits + +#define STATUS 0x07 +#define RX_DR 6 +#define TX_DS 5 +#define MAX_RT 4 +#define RX_P_NO 1 // 3 bits +#define STATUS_TX_FULL 0 + +#define OBSERVE_TX 0x08 +#define PLOS_CNT 4 // 4 bits +#define ARC_CNT 0 // 4 bits + +#define RPD_REG 0x09 +#define RPD 0 + +#define RX_ADDR_P0 0x0A // 5 bytes +#define RX_ADDR_P1 0x0B // 5 bytes +#define RX_ADDR_P2 0x0C // 1 byte +#define RX_ADDR_P3 0x0D // 1 byte +#define RX_ADDR_P4 0x0E // 1 byte +#define RX_ADDR_P5 0x0F // 1 byte + +#define TX_ADDR 0x10 // 5 bytes + +#define RX_PW_P0_REG 0x11 +#define RX_PW_P0 0 // 6 bits +#define RX_PW_P1_REG 0x12 +#define RX_PW_P1 0 // 6 bits +#define RX_PW_P2_REG 0x13 +#define RX_PW_P2 0 // 6 bits +#define RX_PW_P3_REG 0x14 +#define RX_PW_P3 0 // 6 bits +#define RX_PW_P4_REG 0x15 +#define RX_PW_P4 0 // 6 bits +#define RX_PW_P5_REG 0x16 +#define RX_PW_P5 0 // 6 bits +#define RX_PW_MASK 0x3F + +#define FIFO_STATUS 0x17 +#define TX_REUSE 6 +#define TX_FULL 5 +#define TX_EMPTY 4 +#define RX_FULL 1 +#define RX_EMPTY 0 + +#define DYNPD 0x1C +#define DPL_P5 5 +#define DPL_P4 4 +#define DPL_P3 3 +#define DPL_P2 2 +#define DPL_P1 1 +#define DPL_P0 0 + +#define FEATURE 0x1D +#define EN_DPL 2 +#define EN_ACK_PAY 1 +#define EN_DYN_ACK 0 + +#define R_REGISTER 0x00 +#define W_REGISTER 0x20 +#define REG_MASK 0x1F +#define R_RX_PAYLOAD 0x61 +#define W_TX_PAYLOAD 0xA0 +#define FLUSH_TX 0xE1 +#define FLUSH_RX 0xE2 +#define REUSE_TX_PL 0xE3 +#define R_RX_PL_WID 0x60 +#define W_ACK_PAYLOAD 0xA8 +#define W_ACK_PAYLOAD_MASK 0x07 +#define PIPE_0 0x00 +#define PIPE_1 0x01 +#define PIPE_2 0x02 +#define PIPE_3 0x03 +#define PIPE_4 0x04 +#define PIPE_5 0x05 +#define W_TX_PAYLOAD_NOACK 0xB0 +#define NOP 0xFF // TODO diff --git a/rf24/rf24.c b/rf24/rf24.c index 53ae2b4..07e944e 100644 --- a/rf24/rf24.c +++ b/rf24/rf24.c @@ -11,12 +11,14 @@ const unsigned char RF24_STANDBY_2 = 3; const unsigned char RF24_TX = 4; const unsigned char RF24_RX = 5; -unsigned char _ce, _csn, _sck, _mo, _mi, _irq; +unsigned char _ce, _csn, _sck, _mo, _mi, _irq, _payload_len; +void rf24_serial_transmit(unsigned char*, unsigned char); unsigned char rf24_serial_write(unsigned char); void rf24_init(unsigned char ce, unsigned char csn, unsigned char sck, unsigned char mo, unsigned char mi, unsigned char irq){ pin_mode(ce, OUTPUT); + digital_write(ce, LOW); // disable pin_mode(csn, OUTPUT); digital_write(csn, HIGH); // disable pin_mode(sck, OUTPUT); @@ -31,25 +33,74 @@ void rf24_init(unsigned char ce, unsigned char csn, unsigned char sck, unsigned _mi = mi; _irq = irq; - rf24_mode(RF24_POWER_DOWN); + //rf24_mode(RF24_POWER_DOWN); } -void rf24_mode(unsigned char mode){ +// channel in 1Mhz steps +void rf24_config(unsigned char channel, unsigned char payload_len){ + _payload_len = payload_len; + + rf24_config_register(RF_CH, channel&RF_CH_MASK); // 2.4Ghz + channel*1Mhz + + rf24_config_register(RX_PW_P0, 0x00); // auto ACK + rf24_config_register(RX_PW_P1, payload_len&RX_PW_MASK); // data + rf24_config_register(RX_PW_P2, 0x00); // unused... + rf24_config_register(RX_PW_P3, 0x00); + rf24_config_register(RX_PW_P4, 0x00); + rf24_config_register(RX_PW_P5, 0x00); + + // low transmission rate, 0dBm + rf24_config_register(RF_SETUP, (1<